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| HA5351 Data Sheet May 1999 File Number 3690.7 64ns Sample and Hold Amplifier The HA5351 is a fast acquisition, wide bandwidth sample and hold amplifier, built with the Intersil HBC-10 BiCMOS process. This sample and hold amplifier offers a combination of desirable features; fast acquisition time (70ns to 0.01% maximum), excellent DC precision and extremely low power dissipation, making it ideal for use in systems that sample multiple signals and require low power. The HA5351 is in an open loop configuration with fully differential inputs providing flexibility for user defined feedback. In unity gain the HA5351 is completely selfcontained and requires no external components. The onchip 15pF hold capacitor is completely isolated to minimizing droop rate and reduce sensitivity to pedestal error. The HA5351 is available in 8 lead PDIP and SOIC packages for minimizing board space and ease of layout. Features * Fast Acquisition to 0.01% . . . . . . . . . . . . . . . . . 70ns (Max) * Low Offset Error . . . . . . . . . . . . . . . . . . . . . . . 2mV (Max) * Low Pedestal Error . . . . . . . . . . . . . . . . . . . . 10mV (Max) * Low Droop Rate . . . . . . . . . . . . . . . . . . . . . . 2V/s (Max) * Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . . 40MHz * Low Power Dissipation . . . . . . . . . . . . . . . 220mW (Max) * Total Harmonic Distortion (Hold Mode) . . . . . . . . . -72dBc - (VIN = 5VP-P at 1MHz) * Fully Differential Inputs * On Chip Hold Capacitor Applications * Synchronous Sampling * Wide Bandwidth A/D Conversion * Deglitching * Peak Detection * High Speed DC Restore Ordering Information PART NUMBER (BRAND) HA5351IP HA5351IB (H5351) TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld SOIC PKG. NO. E8.3 M8.15 Functional Diagram V+ 6 V3 15pF 8 + GM 1 +IN 5 BUFFER HA5351 7 GND + Pinout HA5351 (PDIP, SOIC) TOP VIEW) +IN NC 4 OUT VOUT 1 2 3 4 8 7 6 5 -IN GND V+ S/H CTRL -IN AV S/H 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 HA5351 Absolute Maximum Ratings Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . +11V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Voltage Between Sample and Hold Control and Ground . . . . . +5.5V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . 37mA Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Test Conditions: VSUPPLY = 5V; CH = Internal = 15pF, Digital Input: VIL = fc0V (Sample), VIH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified TEMP. (oC) HA5351I MIN TYP MAX UNITS PARAMETER INPUT CHARACTERISTICS Input Voltage Range Input Resistance (Note 2) Input Capacitance Input Offset Voltage TEST CONDITIONS Full 25 25 25 Full -2.5 100 -2 -3.0 -1.5 -2.5 60 500 15 2.5 80 +2.5 5 2 3.0 5 +1.5 +2.5 - V k pF mV mV V/oC A A V dB Offset Voltage Temperature Coefficient Bias Current Offset Current Common Mode Range Common Mode Rejection Ratio TRANSFER CHARACTERISTICS Large Signal Voltage Gain VOUT = 2.5V 2.5V, Note 3 Full Full Full Full Full 25 Full 95 85 - 108 40 - dB dB MHz Unity Gain -3dB Bandwidth TRANSIENT RESPONSE Rise Time Overshoot Slew Rate DIGITAL INPUT CHARACTERISTICS Input Voltage VIH 200mV Step 200mV Step 5V Step 25 25 25 Full 0 88 8.5 105 30 - ns % V/s 25, 85 -40 2.1 2.4 0 -1.0 -1.0 - 5.0 5.0 0.8 1.0 1.0 V V V A A VIL Input Current VIL = 0V VIH = 5V OUTPUT CHARACTERISTICS Output Voltage Output Current RL = 510 RL = 100 Full Full Full Full 25, 85 -40 -3.0 20 15 25 - +3.0 - V mA mA 2 HA5351 Electrical Specifications Test Conditions: VSUPPLY = 5V; CH = Internal = 15pF, Digital Input: VIL = fc0V (Sample), VIH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified (Continued) TEMP. (oC) Full 25 25 25 HA5351I MIN TYP 13 0.02 325 325 MAX UNITS MHz VRMS VRMS PARAMETER Full Power Bandwidth Output Resistance Total Output Noise (DC to 10MHz) DISTORTION CHARACTERISTICS SAMPLE MODE Total Harmonic Distortion TEST CONDITIONS 5VP-P, AV = +1, -3dB Hold Mode Sample Mode Hold Mode VIN = 4.5VP-P, fIN = 100kHz VIN = 5VP-P, fIN = 1MHz VIN = 1VP-P, fIN = 10MHz 25 25 25 25 - -80 -74 -57 73 - dBc dBc dBc dB Signal to Noise Ratio (RMS Signal to RMS Noise) HOLD MODE (50% Duty Cycle S/H) Total Harmonic Distortion VIN = 4.5VP-P, fIN = 100kHz VIN = 4.5VP-P, fIN = 100kHz, fS 100kHz VIN = 5VP-P, fIN = 1MHz, fS 1MHz VIN = 1VP-P, fIN = 10MHz, fS 1MHz 25 25 25 25 - -78 -72 -51 70 - dBc dBc dBc dB Signal to Noise Ratio (RMS Signal to RMS Noise) SAMPLE AND HOLD CHARACTERISTICS Acquisition Time VIN = 4.5VP-P, fIN = 100kHz, fS 100kHz 0V to 2.0V Step to 1mV 0V to 2.0V Step to 0.01% (200V) -2.5V to +2.5V Step to 0.01% (500V) 25 25 25 25 Full -2 -10 - 53 64 90 0.3 50 72 +1 10 10 70 100 2 +10 20 ns ns ns V/s V/s mV ns dB ns ns ps Droop Rate Hold Step Error Hold Mode Settling Time Hold Mode Feedthrough EADT (Effective Aperture Delay Time) Aperture Time (Note 2) Aperture Uncertainty POWER SUPPLY CHARACTERISTICS Positive Supply Current Negative Supply Current PSRR NOTES: VIL = 0V, VIH = 4.0V, tR = 5ns To 1mV 5VP-P, 500kHz, Sine Full 25 25 25 25 25 Full Full 10% Delta Full 60 20 20 74 22 22 - mA mA dB 2. Derived from Computer Simulation only, not tested. 3. +CMRR is measured from 0V to +2.5V, -CMRR is measured from 0V to -2.5V. 3 HA5351 Typical Performance Curves 2 OUTPUT (V) OUTPUT (V) 0 100 200 300 TIME (ns) 400 500 0.1 0 0.0 -2 -0.1 200 400 TIME (ns) 600 FIGURE 1. LARGE SIGNAL RESPONSE FIGURE 2. SMALL SIGNAL RESPONSE 2 60 0 40 GAIN (dB) -2 40.163156MHz -3dB GAIN (dB) GAIN 0dB AT 21.34MHz 20 0 -30 -60 0 -6 -20 -8 100K 1M 10M 100M 1K 10K 100K PHASE -119.86 DEG 1M 10M -90 -120 -150 -180 100M PHASE (DEGREES) 6 -4 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 3. UNITY GAIN FREQUENCY RESPONSE FIGURE 4. CLOSED LOOP GAIN/PHASE AV = +1000 2 60 200mVP-P -3dB BANDWIDTH (MHz) 50 13.241189MHz -3dB 40 30 20 10 0 3.5 4 TYPICAL UNITS 0 GAIN (dB) -2 -4 -6 -8 10K 100K 1M FREQUENCY (Hz) 10M 100M 4 4.5 5 SUPPLY VOLTAGE (V) 5.5 FIGURE 5. 5VP-P FULL POWER FREQUENCY RESPONSE FIGURE 6. -3dB BANDWIDTH vs SUPPLY VOLTAGE 4 HA5351 Typical Performance Curves 0.5 3 TYPICAL UNITS 150 0.4 DROOP RATE (V/s) 140 SLEW RATE (V/s) UNIT #1 130 120 110 UNIT #2 100 0.1 90 0 -50 80 -50 UNIT #3 0.3 (Continued) 160 3 TYPICAL UNITS +SLEW RATE -SLEW RATE 0.2 0 50 TEMPERATURE (oC) 100 0 50 TEMPERATURE (oC) 100 FIGURE 7. DROOP RATE vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE 9 4 TYPICAL UNITS HOLD MODE SETTLING TIME (ns) 65 4 TYPICAL UNITS 60 55 50 45 40 35 30 -50 8 RISE TIME (ns) 7 6 5 4 -50 0 50 TEMPERATURE (oC) 100 0 50 TEMPERATURE (oC) 100 FIGURE 9. RISE TIME vs TEMPERATURE FIGURE 10. HOLD MODE SETTLING vs TEMPERATURE 3 0V TO 4V S/H CTRL 0.01 2 PEDESTAL ERROR (mV) OUTPUT 1 S/H CONTROL (V) OUTPUT (V) 10 0.00 S/H CONTROL 67.25ns 5 0 -1 0 -2 0 10 20 30 40 50 TIME (ns) S/H CONTROL RISE TIME (ns) -0.01 3.0E-7 FIGURE 11. PEDESTAL vs S/H CONTROL RISE TIME FIGURE 12. ACQUISITION TIME (0.01%, 0V TO 2V STEP) 5 HA5351 Typical Performance Curves (Continued) OUTPUT 0.02 10 OUTPUT (V) S/H CONTROL (V) 0.00 -0.02 5 -0.04 51.4 ns 0 0 20 40 TIME (ns) 60 80 FIGURE 13. HOLD MODE SETTLING TIME (200V) Die Characteristics DIE DIMENSIONS: 2530m x 1760m x 525m 100 mils x 69 mils x 19 mils METALLIZATION: Type: Metal 1: AlSiCu/TiW Thickness: Metal 1: 6kA 750A Type: Metal 2: AlSiCu Thickness: Metal 2: 16kA 1.1kA PASSIVATION: Type: Sandwich Passivation Nitride - 4kA, Undoped Si Glass (USG) - 8kA, Total - 12kA 2kA SUBSTRATE POTENTIAL: VTRANSISTOR COUNT: 156 Metallization Mask Layout GND GND GND HA5351 V+ V+ V+ S/H CONTROL -IN VOUT VOUT +IN V- V- V- 6 HA5351 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M e D1 A1 eC C A BS A2 L A C L eA C eB E A A1 A2 B B1 C D D1 E -C- NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 7 HA5351 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 L A1 B C D E A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 8 |
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